The startup process of an Intel SoC FPGA (System on Chip Field-Programmable Gate Array) involves a series of steps that initialize the hardware, load the firmware, and boot the operating system (if applicable). Intel SoC FPGAs, such as those in the Cyclone V or Arria 10 families, combine a dual-core ARM Cortex-A processor with FPGA fabric, making the startup process more complex than traditional FPGAs or standalone processors. Below is a detailed explanation of the startup process:

1. Power-On Reset (POR)
Description: When power is applied to the Intel SoC FPGA, the Power-On Reset (POR) circuit initializes the hardware.

Steps:

1. The POR circuit ensures that the voltage levels stabilize.
2. The reset signal is asserted, initializing all registers and logic to their default states.
3. The FPGA fabric and the ARM processor are held in reset until the system is ready to start.

2. Boot ROM Execution
Description: The ARM processor begins executing code from the on-chip Boot ROM.

Steps:

1. The Boot ROM contains the first-stage bootloader (FSBL), which is responsible for initializing critical hardware components.
2. The Boot ROM configures the clock, memory controller, and other essential peripherals.
3. It determines the boot source (e.g., SD card, QSPI flash, or Ethernet) based on the boot mode pins or configuration settings.

3. First-Stage Bootloader (FSBL)
Description: The FSBL is loaded from the Boot ROM or external memory and initializes the system further.

Steps:

1. The FSBL sets up the memory controller to access external DDR memory.
2. It initializes the FPGA fabric by loading the FPGA configuration bitstream (if required).
3. The FSBL loads the second-stage bootloader (SSBL) or the operating system (OS) into memory.

4. FPGA Configuration
Description: The FPGA fabric is configured using a bitstream file.

Steps:

1. The FSBL or SSBL loads the FPGA configuration bitstream from a non-volatile storage device (e.g., QSPI flash or SD card).
2. The bitstream is transferred to the FPGA configuration controller, which programs the FPGA fabric.
3. Once the FPGA is configured, it is ready to execute custom logic.

5. Second-Stage Bootloader (SSBL)
Description: The SSBL (e.g., U-Boot) is responsible for loading the operating system or application software.

Steps:

1. The SSBL initializes additional hardware peripherals (e.g., USB, Ethernet).
2. It loads the operating system kernel (e.g., Linux) or application software from storage (e.g., SD card, eMMC, or NAND flash).
3. The SSBL passes control to the operating system or application.

6. Operating System Boot (Optional)
Description: If an operating system (e.g., Linux) is used, it is loaded and executed.

Steps:

1. The kernel is decompressed and loaded into memory.
2. The kernel initializes the system, mounts the root filesystem, and starts user-space applications.
3. The FPGA fabric and ARM processor work together to execute the application.

7. Application Execution
Description: The system is ready to execute the application software.

Steps:

1. The ARM processor runs the application code.
2. The FPGA fabric executes custom logic, interfacing with the ARM processor via bridges (e.g., HPS-to-FPGA or FPGA-to-HPS bridges).
3. The system operates as designed, with the ARM processor and FPGA fabric working in tandem.

Boot Sources
Intel SoC FPGAs support multiple boot sources, which can be selected using boot mode pins or configuration settings:

• QSPI Flash: Stores the FSBL, FPGA bitstream, and SSBL.
• SD Card: Commonly used for booting Linux or other operating systems.
• Ethernet: Enables network booting (e.g., using TFTP).
• NAND Flash: Stores the bootloader and operating system.
• JTAG: Used for debugging and programming during development.

Key Components in the Startup Process

• Boot ROM: Contains the initial bootloader and hardware initialization code.
• FSBL: Initializes the system and loads the FPGA bitstream or SSBL.
• SSBL: Loads the operating system or application software.
• FPGA Configuration Controller: Programs the FPGA fabric using the bitstream.
• ARM Cortex-A Processor: Executes the bootloader and application software.
• FPGA Fabric: Executes custom logic after configuration.

Example: Boot Process for Intel Cyclone V SoC

1. Power-On Reset: The system resets and initializes.
2. Boot ROM Execution: The ARM processor executes the Boot ROM code.
3. FSBL Execution: The FSBL initializes DDR memory and loads the FPGA bitstream.
4. FPGA Configuration: The FPGA fabric is configured using the bitstream.
5. SSBL Execution: U-Boot loads the Linux kernel from the SD card.
6. Linux Boot: The kernel initializes the system and starts user-space applications.
7. Application Execution: The ARM processor and FPGA fabric run the application.

Debugging the Startup Process

• JTAG Debugging: Use a JTAG interface to debug the bootloader and FPGA configuration.
• Serial Console: Connect to the UART interface to view boot messages.
• LEDs and GPIOs: Use LEDs or GPIOs to indicate the boot progress.

Conclusion

The startup process of an Intel SoC FPGA involves a sequence of steps that initialize the hardware, configure the FPGA fabric, and boot the operating system or application software. Understanding this process is essential for developing and debugging systems based on Intel SoC FPGAs. By leveraging the flexibility of the ARM processor and FPGA fabric, developers can create highly customized and efficient embedded systems.